EFFICIENT FIXED-POINT DLMS ADAPTIVE FILTER FOR LOW ADAPTATION-DELAY AREA-DELAY POWER.

Abstract

Multiplication of a variable by a set of constants, generally known as Multiple Constant Multiplications (MCM), is essential in many Digital Signal Processing (DSP) applications such as, digital Finite Impulse Response (FIR) filters, Fast Fourier Transforms (FFT), and Discrete Cosine Transforms (DCT). An important objective is the reduction of the adder depth (AD), which is defined as the number of adder stages needed to compute a coefficient. In this paper, an efficient architecture for the implementation of a [DLMS] DELAYED LEAST MEAN SQUARE Adaptive Filter. For achieving lower adaptation-delay and area-delay-power efficient implementation, work modifies a novel partial product generator and proposes a strategy for optimized balanced pipelining across the time-consuming combinational blocks of the structure. From synthesis results, it is identified that the proposed design offers nearly 17% less area-delay product (ADP) and nearly 14% less energy-delay product (EDP) than the best of the existing systolic structures, on average, for filter lengths N=8, 16, and 32. This work proposes an efficient fixed-point implementation scheme of the proposed architecture, and derives the expression for steady-state error. This Work show that the steady-state mean squared error obtained from the analytical result matches with the simulation result. Moreover, we have proposed a bit-level pruning of the proposed architecture, which provides nearly 20% saving in ADP and 9% saving in EDP over the proposed structure before pruning without noticeable degradation of steady-state-error performance