Investigation on Signed Modulo Multipliers for RNS Applications using FPGAs.

Abstract

The RNS has been considered as an interesting theoretical topic for researchers in recent years because of its ability to reduce the Hardware complexity compared to other counter parts such as binary number system which has direct proportionality between width(input bitlength) and hardware requirement. Its importance stems from the absence of carry propagation between its arithmetic units. This facilitates the realization of high-speed, low-power arithmetic. The modulo 2n multiplier is assumed to be simplest among the special module set, is taken into consideration and analysis have been made as a comparative prescriptive with normal modified booth multiplier under Radix-4(22).Investigation have been made on the VLSI constrain by forcing the same input among the Ordinary Modified booth Encoder Multiplier and modulo 2n multiplier and comparative performance parameter are analyzed, and on the conclusion obtained ,future recommendations have been made for multi-modulo multiplier.