A Review of an Efficient 8-bit Vedic Multiplier using Reversible Logic

  • Abhilasha * Reva Institute of Technology and Management Bangalore
  • Mr. Sudharshan K M Reva Institute of Technology and Management Bangalore
DOI: https://doi.org/10.53555/eee.v1i5.397
Keywords: -Multiplier, Nikhilam sutra algorithm, Vedic multiplier, Xilinx, FPGA

Abstract

This paper basically emphasizes on different methodologies that have been proposed from past few years on multiplier. Research on multiplier and reversible logic has widely covered applications such as design of ALU, RISC, CISC, Design of low power arithmetic and data path for digital signal processing (DSP), Low power CMOS, Optical computing, Quantum computing, Nanotechnology and many more .These applications led to untiring efforts for further techniques yet to be proposed. This paper enlightens us about numerous techniques that have extensively being used for Vedic multiplier based Nikhil am sutra using reversible logic.

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Author Biographies

Abhilasha *, Reva Institute of Technology and Management Bangalore

PG Student Dept. of ECE 

Mr. Sudharshan K M, Reva Institute of Technology and Management Bangalore

Department of ECE

Published
2015-05-31
How to Cite
*, A., & K M, M. S. (2015). A Review of an Efficient 8-bit Vedic Multiplier using Reversible Logic. IJRDO - Journal of Electrical And Electronics Engineering, 1(5). https://doi.org/10.53555/eee.v1i5.397
Issue
Vol. 1 No. 5 (2015): IJRDO - Journal of Electrical And Electronics Engineering
Section
Articles

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