Low Power SRAM design by Charge-Recycling assist Technique operating in Near Threshold voltage using 14nm Finfet Technology
This paper proposes a chargerecycling SRAM circuit design by using read and write assist scheme, the wasted charge in conventional read assist circuit can be efficiently recycled in write assist technique. The aim is to reduce the dynamic power consumption of SRAM assist technique using Near-Threshold voltage (NTV) operation in 14nm FinFET Technology. Although nearthreshold voltage operation is an attractive means of achieving high energy efficiency, it can degrade the circuit stability of static random access memory (SRAM) cells. To reduce the Vth variations, fin-shaped fieldeffect transistors are used to reduce the random dopant fluctuation, which is a major contributor to Vth variations, using an undoped channel. Here, 7T SRAM cell consume low power when compared to other conventional 8T and 10T SRAM cell due to its single bitline structure. Thus the proposed SRAM circuit consume Less Power by operating it in NTV region.
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